Vlsi Implementation Of Low Power Barrel Shifter Using Complex Logic Structures

The purpose of this paper is to design the barrel shifter using various logic structures to optimize the power. The barrel shifter is mostly use in ALU for shift operation and shifting of data. This barrel shifter can be use for fastening the processor speed. This work evaluates VLSI design of barrel shifter on 250nm, 180nm and 50nm MOS technology. Barrel shifter is designed by Pseudo NMOS logic, Dynamic logic, and Domino logic. All the simulations are done on Tanner EDA 13.2 tool. It is design to obtain the power consumed by each design and propose the low power design to optimize the ALU power. The results of simulation are compared and suggest the best design. Three generation of CMOS technology is use to show the difference between powers dissipated.
At the end, propose low power barrel shifter with suitable logic structure is given. The use of various technology files helps to reduce design area, power and increase speed of operation.
Key words' Barrel Shifter Dynamic logic, Domino logic, Pseudo NMOS logic, Low power, Tanner EDA Tool.
Barrel shifter is one of the major components in ALU. Barrel shifter is often used for shifting operation like shift right logical, shift left logical, shift left arithmetic, shift right arithmetic, right rotate, left rotate. The architecture of barrel shifter can be designed by using 2:1, 4:1, 8:1, Mux trees[6]. Barrel shifter is most essential element in DSP applications[3].
Barrel shifter is designed using Mux trees to use it in repetitive form so that power consumed by the barrel shifter should minimum. Our work is divided into two sections. At first, the Multiplexers are designed with complex logic structure on all three technology files. And secondly, by using these Mux blocks barrel shifter is designed on 250nm, 180nm and 50nm technology. Complex logic structure involves following techniques (1) Pseudo NMOS (2)Domino logic (3)Dynamic Logic. Result comprises of comparison of both technology techniques and simulation of above all logics which shows the optimized power and area which is helpful in low power ALU design.

Barrel shifter is combinational logic circuit with 'n' number of data inputs and data outputs and set of control inputs which are used to perform shifting operation as shown in fig 1. Barrel shifter is designed using Multiplexers. Barrel shifter design is for natural size like (2,4,16).This project is done on 8 bit barrel shifter which can Shift input by 0,1,2,3,4,5,6,7, bit. Four select lines are used as it is 8 bit barrel shifter i.e. S0, S1, S3. Basically barrel shifter is used with logical left shift operation which is controlled by select inputs. Select lines are used to specify the amount of shift only, For example, if the input bits are 10011 where each bit represent single bit information and select line (control line) is 000 (0), then the output is 10000. It is designed using three types of complex logic structures which are efficient in reducing the power consumption of the barrel shifter. These logic styles are as given below.
Fig.1 Design of Barrel Shifter using 2:1 Multiplexers
Truth table
Sr. No. Input bit stream control signal Output
1 01110011 000 10000000
2 01110011 010 0110000
3 01110011 011 11100110
4 01110011 111 01110011
Table.1 Truth Table of Barrel Shifter
A. Pseudo NMOS logic
In pseudo NMOS logic all the pull up network is replaced by single PMOS. Here the load device is single P transistor with gate connected to ground. So the area required is less than that of the static complementary network. The gain of the pull up has to decrease to provide the adequate noise margin. The construction diagram of the pseudo NMOS logic is as shown in fig 2.

Fig.2 Schematic Design of 2:1 MUX Using Pseudo NMOS Logic
B. Dynamic logic
The dynamic logic style consist of pull down network same as the complementary logic. The operation of this circuit is divided into two phases: Precharge and evaluation, with mode of operation determined by clock cycle. The dynamic logic is most widely used as its gates have faster switching speed because of reduced load capacitance. The construction diagram of 2:1 Mux using dynamic logic is as shown in fig 3.

Fig.3 Schematic Design of 2:1 Mux using Dynamic Logic
C. Domino logic
Domino logic consists of special form of CMOS with inverting buffer at the output terminal. It is also operated during two phases i.e. precharge and evaluation[8]. Drawback of the precharged nodes in dynamic logic is removed by placing the inverter at the output of each gate. All the inputs of pull down network are at zero logic level during the precharge period and remain at zero logic level until the evaluation stage. The construction diagram of domino logic is as shown below in fig 4.

Fig.4 Schematic Design of 2:1 Barrel Shifter using Domino Logic
We analyzed all the technology files and stimulated all the three logic styles. In Pseudo NMOS Logic style single PMOS is used which is connected Vss (logic 0). Hence during the switching time PMOS is continuously ON, So that more Leakage current continuously appeared at output terminal. Due to leakage current, power consumed by the circuit is more. In dynamic logic style PMOS and NMOS are used with Pull down network. As common clock pulse is given to the both PMOS and NMOS, It removes the drawback of Pseudo NMOS logic. Therefore we can switch both devices as per requirement hence power consumption is less. In domino logic style the circuit is same as the dynamic logic except inverting buffer.

A. Advantages.
' Domino circuits are fast and draw no quiescent power.
' No glitches on output but they require a reasonable clock pulse
' Only single clock pulse is required to activate all the circuitry.

The schematic diagram of barrel shifter using Tanner EDA S-Edit tool as shown in fig.

Fig.5 Schematic Design of Proposed Barrel Shifter

A 8 bit barrel shifter is designed and simulated using the Tanner EDA 13.2 tool at 250nm,180nm,50nm CMOS technology at VDD level 5V, 3.3V, 0.6V respectively[2]. It performs left shift operation with adding zero.

B. Power Analysis of Barrel shifter
The total Power in CMOS technology is given by following Equation 1.
Total power = Static Power + Dynamic power + Short
Circuit power
Pt = P static + P dynamic + P short circuit (1)

Static power is power dissipated when the current flows between the supply rails in the absence of switching activity.
In dynamic power dissipation, each time capacitor CL charged through PMOS transistor, its voltage rises from 0 to VDD, and certain amount of energy is drawn from power supply, part of energy is stored in the PMOS, and remaining is stored in capacitor[5].The dynamic average power can be given by following equation.

Pave = CL Vdd2 f Where, f =1/ T (2)
Short circuit power is a power dissipated when the current flows through brief transient when both pull up and pull down devices both conduct at same time where one or both devices are in saturation.
Power analysis of 8 bit barrel shifter is done using three technology files of 250nm, 180nm and 50nm as function of VDD at 5V, 3.3V, 1V respectively [2]. The power dissipated by the 8 bit barrel shifter is as shown in the table 2.
Power (Watt)
Technology Files Pseudo NMOS Logic Dynamic Logic Domino Logic
250 nm 1.8610x10-01 4.1991x10-03 3.1341x10-03
180 nm 1.1158x10-01 1.5337x10-03 1.1036x10-03
50 nm 1.9282x10-03 4.3167x10-06 3.9659x10-06
Table 2 Power Analysis

Area plays a vital role in digital circuit applications. The number of MOS required in each logic structure is given below in table 3. According to the table 3 the Number of MOS are reduced in Pseudo NMOS logic which is up to 120 for 8-bit barrel shifter than in other two logic structures.
Design Number of MOS
Pseudo NMOS Logic Dynamic Logic Domino Logic
2:1 MUX 5 6 8
8-Bit Barrel Shifter 120 144 192
Table 3 Area Analysis
The power analysis is carried on 8 bit barrel shifter which is designed using Pseudo NMOS logic, Dynamic logic, Domino Logic structures on TSPC 250nm,180nm & 50nm file over the transient time period of 1000 nanoseconds with respect to VDD = 5V, VDD = 3.3V & VDD=0.6V respectively. The Average power dissipated by the barrel shifter is shown in Graph 1 and Table 2.
Graph 1 Power Analysis

Barrel Shifter can be designed using various combinational logic circuits such as logic gates, decoder, multiplexers etc. above paper describe design of functional block i.e. multiplexer using different complex logic structures to reduce the Power of barrel shifter and ALU. The existing and proposed Barrel shifter consist of Domino logic which eventually reduces the power of the circuit.

[1] Neil H.E. Weste, Kamran Eshraghian, 'Principles of CMOS VLSI Design' Second edition
[2] Meetu, Mehrishi, S. K. Lenka 'VLSI design of low power ALU using optimized barrel shifter', vol. 2 Issue 03, May-June 2013 International journal of VLSI and Embedded systems.
[3] Abhijit asati and Chandrashekhar, 'VLSI implementation of high performance barrel shifter architecture using three different logic styles,' in International journal of recent trends in engineering Vol.2, No.7, November 2009.
[4] John F. Wakerly, 'Combinational design Examples,' Chapter 6 1999.
[5] http://www.ee.iitb.ac.in/uma/~hits/sevan/chapter5
[6] Rinu papachan, V. Vijaykumar, T.Ravi,'Design analysis of 4 bit low power barrel shifter in 20nm FINFET technology' the International journal of Engineering and science (Ijes) vol.2 Issue 3 2013.
[7] CMOS Digital Integrated Circuits: Analysis and Design ' S. Kang, Y.Leblebici, McGraw-Hill.
[8] elearning.vtu.ac.in/11/enotes/CMOS_VLSI_DES/Unit5-PN'
[9] bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter6
[10] Priyanka Mandal,Sidhant Malani, Yogesh Gudhekar, Suparas singhi and P.M.palsodkar 'VLSI implementation of a Barrel Shifter',Vol.2,150, Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India

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